1. Field of the Invention
This invention relates to a-current-mode switching power supply.
2. Description of the Related Art
FIG. 11 is a block diagram of an example of a current-mode switching power supply of the prior art. Here 1 is an input terminal, to which the input voltage VIN of the switching power supply is input; Mp is a P-channel MOS transistor, which is a switching element; Mn is an N-channel MOS transistor, which is a synchronous rectifying element; and the two transistors Mp and Mn are driven by respective driving circuits 2 and 3 so as to be turned on and off in alternation. A smoothing filter, comprising a series circuit of an inductor L and output capacitor Co, is connected to the connection point of the transistors Mp and Mn. By turning on and off in alternation the transistors Mp and Mn connected to the input voltage VIN, the intermittent voltage occurring at the connection point is smoothed by the smoothing circuit comprising the inductor L and output capacitor Co, so that the desired output voltage VOUT is output from the output terminal 4. The output voltage VOUT is divided by the resistors R1 and R2, for input to the inverting-input terminal of an error amplifier ERRAMP. A reference voltage VREF (for convenience, the same name as the circuit is used), corresponding to a target voltage, output from a reference voltage circuit VREF, is input to the non-inverting input terminal of the error amplifier ERRAMP. Further, a phase compensation circuit, comprising a series circuit of a resistor Rc and capacitor Cc, is connected between the output terminal and the inverting input terminal of the error amplifier ERRAMP. By means of this configuration, the error amplifier ERRAMP outputs an error signal according to the difference between the output voltage and the target voltage. Below, this error signal is called a feedback signal FB. The feedback signal FB is input to the inverting input terminal of a PWM comparator PWMCMP, the output signal of which is input to the reset terminal R of an RS flip-flop 5. A signal OSC from an input terminal 6 is input to the set input terminal S of the RS flip-flop 5, and the flip-flop 5 is set by the signal OSC at each prescribed interval so that the Q output goes to H (high).
The current flowing in the switching element Mp is detected by current detection means 7, the current detection signal is added to a slope compensation signal output from a slope compensation circuit 8 by an adder circuit 9, and the result is input to the non-inverting input terminal of the PWM comparator PWMCMP. The slope compensation circuit 8 is also started by the signal OSC at prescribed intervals. The flip-flop Q output is input as a PWM signal to the driving circuits 2 and 3, so that when the flip-flop Q output is H the switching element Mp is on, and when the flip-flop Q output is L (low) the synchronous rectifying element Mn is on. This method, in which the current flowing in the switching element Mp is detected and the switching element is controlled, is called the current mode. It is known that, in a current-mode switching power supply, when the switching element is made to operate at an on-duty (time fraction) of 50% or higher, a phenomenon called subharmonic oscillation occurs, in which there is oscillation at a frequency lower than the switching frequency (see for example Japanese Patent Laid-open No. 2004-40856). The slope compensation circuit 8 prevents this. By adding to the current detection signal a monotonically increasing slope compensation signal output from the slope compensation circuit 8, to raise the slope (rate of increase) of the current detection signal, subharmonic oscillation is prevented.
FIG. 12 shows an example of the configurations of the current detection means 7, slope compensation circuit 8, and adder circuit 9. The driving circuit 2 and transistor Mp are the same as those in FIG. 11, and Rs is a sense resistor for detection of the current flowing in the switching element Mp. The voltages at both terminals of the sense resistor Rs are level-shifted by the level-shift circuits 10 and 11 and are input to the transconductance amplifier 12. Various designs can be applied as level-shift circuits 10 and 11, but a simple configuration, such as for example a voltage divider circuit, may be used. The transconductance amplifier 12 outputs a current according to the difference between the two inputs. In the case of this invention, the output of the transconductance amplifier 12 is a sink current, which absorbs a larger current for larger differences between the two inputs, that is, for larger currents flowing in the switching element Mp. The sink current Is which is the output of the transconductance amplifier 12 is supplied to the power supply VIN via the P-channel MOS transistor M1. The P-channel MOS transistors M2 and M1 are configured as a current mirror circuit, and current I1 flowing in the P-channel MOS transistor M2 is copied from the output current Is of the transconductance amplifier 12 (is either equal to or is proportional to the current Is). This current I1 is equivalent to a current detection signal which detects the current flowing in the switching element Mp.
By using a constant current source I0 and capacitor C1 to configure an integration circuit, such that the constant current (the value of which is also represented by I0) supplied from the constant current source I0 is integrated by the capacitor C1, the voltages across the capacitor C1 (the integration value) rises linearly. The signal OSC is a signal with a constant period, supplied to this circuit from outside, and a reset signal with a prescribed time width is applied at fixed intervals to the gate of the N-channel MOS transistor M3. The N-channel MOS transistor M3 is a reset transistor which is turned on when the signal OSC is the reset signal H, causing the charge on the capacitor C1 to be discharged and resetting the integration voltage. The integration voltage on capacitor C1 is applied to the gate of the N-channel MOS transistor M4. The N-channel MOS transistor M4 operates as a source-follower circuit, and applies a voltage V1=(integration voltage on capacitor C1−threshold voltage of N-channel MOS transistor M4) to the resistor R3. If the resistance value of resistor R3 is R3, then a current I2=V1/R3 flows in the resistor R3, and I2 also becomes a signal which rises linearly. The P-channel MOS transistors M5 and M6 form a current mirror circuit, and the current I3 flowing in the P-channel MOS transistor M6 copies the current I2. This current I3 is equivalent to a slope compensation signal.
If the currents I1 and I3 both flow in the resistor Ra, and if the resistance value of resistor Ra is Ra, then the voltage Vsig across the resistor Ra which results (one end of the resistor Ra is at GND reference potential, so that this is equal to the voltage Vsig on the other end, connected to the P-channel MOS transistors M2 and M6) as a result is Vsig=Ra×(I1+I3)=Ra×I1+Ra×I3. This voltage Vsig is a signal which combines (is the sum of) the current detection signal and the slope compensation signal, and is a signal used for on/off control of the switching element.
FIG. 13 is a timing chart, used to explain operation of the above circuit. Shown from the top in order are the slope compensation signal (equivalent to the current I3 shown in FIG. 12), which is the output of the slope compensation circuit 8; the current detection signal (equivalent to the current I1 in FIG. 12); the combined signal obtained by adding the current detection signal and the slope compensation signal (equivalent to the voltage signal Vsig in FIG. 12); the signal OSC (the signal the H portion of which sets the RS flip-flop 5); the reset signal (output signal of the PWM comparator PWMCMP) of the RS flip-flop 5; and the PWM signal (Q output of the RS flip-flop 5). The signal OSC H level causes the slope compensation circuit 8 to be triggered, so that the slope compensation signal rises (strictly speaking, the signal OSC returns to L, and rises after the integration voltage on the capacitor C1 exceeds the threshold voltage of the N-channel MOS transistor M4), and in addition the RS flip-flop 5 is set, the switching element Mp is turned on, and the current detection signal also rises. The combined signal Vsig which is the output of the adder circuit 9 also rises, and when the combined signal Vsig reaches the level or value of the feedback signal FB which is the output of the error amplifier ERRAMP, the output signal of the PWM comparator PWMCMP goes to H, and the RS flip-flop 5 is reset. When the RS flip-flop 5 is reset, the PWM signal goes to L, the switching element Mp is turned off, and the current detection signal values goes to zero. When the current detection signal becomes zero, the combined signal Vsig becomes a signal which reflects only the slope compensation signal, and the reset signal for the RS flip-flop 5 is canceled. The above operations are repeated upon each period of the signal OSC, to obtain the prescribed output voltage VOUT.
In a current-mode switching power supply if the load is light (the output current is small) and moreover the switching frequency (that is, the frequency of the above signal OSC) is high, then the current detection signal detected by the sense resistance Rs becomes minute. This situation is illustrated in FIG. 14. The signals shown in FIG. 14 are the same as in FIG. 13, but are shown for a case in which the load is light and moreover the switching frequency is high. If the switching frequency is high and the switching period is short, then there must be a balance with the combined signal Vsig which rises in this short switching period (if balance is not achieved, the PWM waveform duty is either too high or too low, the output voltage VOUT changes, and ultimately balance is attained), and compared with cases in which the switching period is long, the output FB of the error amplifier ERRAMP declines. Further, as shown in FIG. 14, if under a light load there is little charge from the output capacitor Co (that is, the output current is small), then the output voltage VOUT increases, so that the feedback signal FB which is output from the error amplifier ERRAMP becomes even smaller. In this way, when under a light load and with-a high switching frequency, the feedback signal FB decreases to near zero, and when the value immediately after the combined signal Vsig, which is a sawtooth wave, begins to rise, is still low, the PWM comparator PWMCMP operates (a reset signal is output to the RS flip-flop 5), so that an erroneous pulse is output as shown in FIG. 14, causing unstable operation. Further, because the feedback signal FB, which is the output of the error amplifier ERRAMP, is minute, the signal is readily affected by noise, and this also gives rise to unstable operation.